The present invention relates to a semiconductor device, and more particularly, to a static random access memory (SRAM) cell and method of manufacturing the same, which are suitable for high packing density and cell stabilization.
FIG. 1A is a plan view of a conventional SRAM. FIG. 1B is an equivalent circuit diagram of FIG. 1A.
Referring to FIGS. 1A and 1B, in the conventional SRAM cell, a wordline W/L acting a, the gate of first and second access transistors TA1 and TA2, and bitlines B/L1 and B/L2 connected to each other through drain area D of access transistors TA1 and TA2 and a contact I4.
Gate G of first and second drive transistors TD1 and TD2 is connected to active area B, that is, source area S, of access transistors TA1 and TA2 via contacts I1 and I2, and simultaneously to a load resistor R through which a power voltage Vcc is supplied. Drain area D of first and second drive transistors TD1 and TD2 is coupled to source area S of first and second access transistors TA1 and TA2 via N+ junction. Source area S of first and second drive transistors TD1 and TD2 is coupled to a conductive line G via contact I3.
In the method of manufacturing the conventional SRAM cell, the gate of transistor made of a first polysilicon layer is formed on a substrate which is divided into a field area A and active area B. Gate G of first and second drive transistors TD1 and TD2 is floated to be in contact with active area B through first contact I1. Gate G of access transistors TA1 and TA2 becomes wordline W/L.
After a first CVD oxide layer is formed on the overall surface of the substrate, a second contact I2 is formed. Then, a second polysilicon layer is deposited and patterned in a form to thereby form conductive line G. A second CVD oxide layer is deposited on the overall surface of the substrate and selectively etched to thereby form a third contact I3. Thereafter, a third polysilicon layer is deposited and patterned to form load resistor R. This load resistor is connected to floating gate G of drive transistors TD1 and TD2 through third contact I3.
A third CVD oxide layer is deposited on the overall surface of the substrate and selectively etched to form a fourth contact I4 on the drain area of access transistors TA1 and TA2. A bitline of metal is formed to be connected to the drain area of access transistors TA1 and TA2 through fourth contact I4. By doing so, a conventional SRAM cell is fabricated.
In the above structure of SRAM cell, the cell is unstable due to asymmetricity and there is a limit in controlling the load resistor. This involves difficulty in controlling cell standby current and in high integration because the cell is large.